1. Field of the Invention
The present invention relates to an integrated circuit, and more particularly, to a frequency doubler circuit implemented in an integrated circuit.
2. Description of the Related Art
Frequency doubling circuits are often used in phase locked loops for synthesizing a clock signal related in phase to an input signal. Frequency doubling of input signals at low frequency can be realized by use of a switching capacitor, a differential amplifier, an emitter-coupled transistor pair having different emitter area ratios (W/L), and using signal delay by logic gates and flip-flops.
At higher frequencies, implementation of frequency doubling of an input signal becomes difficult.
Conventional methods of doubling an input signal having a predetermined frequency in a high-frequency region include using the product of an input signal IN and a quart-shifted signal of the input signal IN, and using a micro strip line having a quarter-wave length of the input signal IN and the second harmonic frequency to the input signal IN.
However, a micro strip line cannot easily be put in an IC without affecting the operations and placement of other components in the IC.
FIG. 1 shows a conventional frequency doubler circuit, having a plurality of amplifiers 11, 13 and 19, a phase shifter 17 and a multiplier 15. The amplifiers 11 and 13 amplify an input signal IN, which operates at a predetermined frequency fo. Signal IN is output from a voltage controlled oscillator (VCO) of a phase locked loop (PLL). Signal I output for amplifier 13 is fed into a phase shifter 17, which phase shifts signal I by xcfx80/2 or 90xc2x0 to form signal Q. Multiplier 15 multiplies I with the xcfx80/2 phase-shifted signal Q. The output of multiplier 15 is a signal having a frequency which is double of frequency fo, i.e., 2fo. This signal is amplified by amplifier 19 and then the amplified signal is applied to a local oscillator (LO) of a mixer.
A problem occurs with the circuit of FIG. 1 when there is a mismatch in the gain of I and Q or a mismatch in the phase between the two signals I and Q. This can result from a change in the processing condition or temperature.
Further, harmonics of the frequency fo and modulated frequency components can result due to non-linearity of active elements. When pumped to an LO (not shown) of a mixer, the harmonics of the doubled frequency signal may adversely affect the sensitivity characteristic of a system.
Accordingly, a need exists for a frequency doubler circuit which is easily implemented in an integrated circuit (IC) and having improved frequency doubling performance at a higher frequency region.
A need also exists for a detect-control unit for improving the frequency doubling performance even when there are changes in the processing condition or temperature.
A frequency doubler circuit is provided, the circuit including a phase shifter, a first buffer, a second buffer, a detect-control unit, a third buffer, a fourth buffer, a multiplier and an output buffer. The phase shifter outputs, in response to an input signal having a predetermined frequency, a first signal which equals to the input signal in phase and a second signal which differs from the input signal in phase. The first buffer filters and buffers the first signal, and the second buffer filters and buffers the second signal. The detect-control unit detects a phase difference between the first and second signals in response to the first signal, the second signal, the output signal of the first buffer and the output signal of the second buffer, and outputs first and second control signals.
The third buffer buffers the output signal of the first buffer in response to the first control signal, and the fourth buffer buffers the output signal of the second buffer in response to the second control signal.
The multiplier multiplies the output signals of the third and fourth buffers. The output buffer buffers the output signal of the multiplier.
Preferably, the second signal differs from the first signal in phase by about 90xc2x0 and the output signal of the fourth buffer differs from the output signal of the third buffer in phase by about 90xc2x0.
Also, preferably, the filters of the first and second buffers are high pass filters, and the output filter of the output buffer is a band pass filter.
To achieve the second object, there is provided a detection controlling apparatus for controlling, in response to an input signal having a predetermined frequency, a first signal which equals to the input signal in phase and a second signal which differs from the input signal in phase, to be multiplied, the detection controlling apparatus including a phase detector, a converter and a driving buffer. The phase detector outputs a voltage which is proportional to a phase difference between the first signal and the second signal in response to the first and second signals. The converter generates current which is proportional to the output voltage in response to the output voltage of the phase detector network. The driving buffer buffers the output signal of the converter in response to the output signals of the first and second buffers, and outputs the first control signal for controlling the third buffer and the second control signal for controlling the fourth buffer.